Low-power Fft via Reduced Precision Redundancy

In this paper, we propose a technique for designing low-power fast Fourier transform (FFT) processors with applications in next generation wireless LAN and wireless access systems. The proposed low-power technique is based on the general principle of soft digital signalprocessing [4] where voltage overscaling (VOS) [4] (scaling the supply voltage beyond the critical voltage vdd-crit required for correct operation) is applied in conjunction with algorithmic noise-tolerance (ANT) techniques. In this paper, we propose an ANT technique referred to as reduced precision redundancy for compensating the degradation in the signal-to-noise ratio (SNR) at an FFT output due to VOS. Simulation results using the proposed scheme with 0.25 ,urn standard CMOS technology show that the power consumption in a butterfly functional unit of an FFT processor can be reduced by 44% over a conventional voltage-scaled system without any S N R loss in the context of a typical orthogonal frequency division multiplexing (OFDM) based WLAN system.